problem de compilation VHDL

Electronique numérique / Circuits logiques programmables EPLD, CPLD, FPGA d'Altera ou de Xilinx VHDL, Verilog ou SystemC

Modérateur : Modérateur

za3im

problem de compilation VHDL

Message par za3im »

Bjs, s'il vous plais aidez moi à corriger les problèmes de copilation du programme suivant:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY moteur IS PORT (
a,b,c: IN std_logic;
T1,T2,T3,T4,T5,T6,T7,T8: OUT std_logic;
etat1,etat2,etat3,etat4,etat5,etat6,etat7,etat8:INOUT std_logic);
END moteur;

ARCHITECTURE behavior OF moteur IS
BEGIN
PROCESS(a,b,c)
BEGIN
-- etat 1
IF (((a='0') AND (b='0') AND (c='0')) or (etat1='1') or (etat2='1') or (etat3='1') or (etat4='1') or (etat5='1') or (etat6='1') or (etat7='1')) THEN
T1<='1';
T2<='1';
T3<='0';
T4<='0';
T5<='1';
T6<='1';
T7<='0';
T8<='0';

-- etat 2
ELSE IF (((a='0') AND (b='0') AND (c='1')) or (etat2='1') or (etat3='1') or (etat4='1') or (etat5='1') or (etat6='1') or (etat7='1')) THEN
T1<='0';
T2<='0';
T3<='0';
T4<='0';
T5<='1';
T6<='1';
T7<='0';
T8<='0';
etat2<='1';

-- etat3
ELSE IF(((a='0') AND (b='1') AND (c='0')) or(etat3='1') or (etat4='1') or (etat5='1') or (etat6='1') or (etat7='1')) THEN
T1<='0';
T2<='0';
T3<='1';
T4<='1';
T5<='1';
T6<='1';
T7<='0';
T8<='0';
etat3<='1';

-- etat4
ELSE IF (((a='0') AND (b='1') AND (c='1')) or (etat4='1') or (etat5='1') or (etat6='1') or (etat7='1')) THEN
T1<='0';
T2<='0';
T3<='1';
T4<='1';
T5<='0';
T6<='0';
T7<='0';
T8<='0';
etat4<='1';

--etat5
ELSE IF (((a='1') AND (b='0') AND (c='0')) or (etat5='1') or (etat6='1') or (etat7='1')) THEN
T1<='0';
T2<='0';
T3<='1';
T4<='1';
T5<='0';
T6<='0';
T7<='1';
T8<='1';
etat5<='1';

--etat6
ELSE IF (((a='1') AND (b='0') AND (c='1')) or (etat6='1') or (etat7='1')) THEN
T1<='0';
T2<='0';
T3<='0';
T4<='0';
T5<='0' ;
T6<='0';
T7<='1';
T8<='1' ;
etat6<='1';

--etat7
ELSE IF (((a='1') AND (b='1') AND (c='0')) or (etat7='1')) THEN
T1<='1';
T2<='1';
T3<='0';
T4<='0';
T5<='0';
T6<='0';
T7<='1';
T8<='1';
etat7<='1';

--etat8
ELSE IF ((a='1') AND (b='1') AND (c='1')) THEN
T1<='1';
T2<='1';
T3<='0';
T4<='0';
T5<='0';
T6<='0';
T7<='0';
T8<='0';
etat1<='1';
END IF;
END PROCESS;
END behavior;
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